1. Technical Field
The present invention relates generally to memory circuits, and more particularly to a memory building block that is scalable.
2. Description of the Related Art
Memory devices typically include a memory core having an array of memory cells for storage and retrieval of data. Today's memory devices typically include at least one memory cell array organized in rows and columns of memory cells. The rows of memory cells are coupled through word lines and the columns of memory cells are coupled through bit lines. Each column can have a single bit line, for single-ended memory cells, or a complementary bit line pair, for dual-ended memory cells. Although many architectures are possible, a row or word line decoder including a plurality of word line drivers and a column decoder are provided for decoding an address for accessing a particular location of the memory array. Address decode circuitry is included to select a word line based upon the value of the address provided to the memory device.
Large memory arrays require large drivers and have high internal delays. In addition, compiled memories that reach large configuration ranges can get very slow and use a lot of power due to the increased driver sizes that are required. A compiled memory is any memory which is built in a manner which allows its expansion while keeping the same general functionality. An example of which would be a single port SRAM memory which may be compiled to support numerous memory sizes between a 16×32 and a 16384×128. In order to produce a very large address space, memory arrays get large which result in long access times for the address space.
FIG. 4 depicts a memory 400 having a single 16K×16 memory array in accordance with the prior art. As is shown, memory 400 includes a single large memory array 402. In order to select the desired location within array 402, decoders with a high output drive are required, such as row decode 404 and column decode 406. Row decode 404 and column decode 406 are used to select the appropriate rows and columns to select the desired locations. Based on this address, memory 400 will produce an output 408. In the illustrated example, a 16K×16 bit memory array is used which will produce a 16 bit output. This prior art memory has a slower access time because of the large array of memory cells. Due to the large physical size of the array, the drivers in the decode logic 404 and 406 must be very large, and the bitline movement during a read access will be very slow due to the inherent low drive strength of the memory's bit cells.
Therefore, a need exists for a method and device for a scalable memory building block that will provide improved access times and will provide large address spaces.